1. Field of the Invention
The present invention relates to a protective circuit, and more particularly to an electrostatic discharge (ESD) protection circuit.
2. Description of the Prior Art
Electrostatic discharge (ESD) is a common phenomenon in semiconductor processes. Excess current brought by ESD enters an IC via an I/O pin for a very short time and destroys the internal circuit of the IC. In order to solve the problem, a protection circuit is usually installed between the internal circuit and the I/O pin. The protection circuit must activate before the pulse of an electrostatic discharge can reach the internal circuit, so as to instantly eliminate the high voltage of the pulse. Consequently, the destruction caused by ESD is reduced.
With the continuing scaling-down of semiconductor integrated circuit (IC) device dimensions, not only are channel lengths being shortened, gate oxide layers becoming thinner, and junction depths becoming shallower, but dopant concentrations of wells are also rising in deep submicron CMOS processes. All of these processes make IC products more susceptible to damage from electrostatic discharge (ESD). Consequently, more effective ESD protection circuits need to be built on-chip to discharge ESD-induced currents, and hence protect the IC against any ESD-related damage. In short, ESD robustness for IC products needs to be improved. To make an effective ESD protection circuit, an adequate ESD protection device must first be designed and manufactured into the ESD protection circuit. A very direct and effective way to increase the discharge path for ESD-induced current may be realized by enlarging the area of ESD protection device. However, the chip area occupied by the ESD protection device should not be excessive, lest the ESD protection device prevents further size reductions to the chip.
The prior art method of preventing electrostatic breakdown caused by electrostatic pulses is using MOSFET parasitic diodes as ESD protection devices. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art ESD protection circuit 20 used to protect an internal circuit 10. The ESD protection circuit 20 is electrically connected to the internal circuit 10 and a bonding pad 12, which is used as a transfer medium between the internal circuit 10 and external electronic signals. When static electricity discharges through the bonding pad 12, the ESD protection circuit 20 can protect the internal circuit 10 from excess electrostatic currents that could burn out the internal circuit 10. The ESD protection circuit 20 comprises a P-type metal-oxide semiconductor (PMOS) 22 and an N-type metal-oxide semiconductor (NMOS) 24. The drains of the PMOS 22 and NMOS 24 are tied together and electrically connected to the internal circuit 10 and the bonding pad 12 by a conducting wire 14. The source of the PMOS 22 is connected to both the gate of the PMOS 22 and a VDD power terminal. The source of the NMOS 24 is connected to both the gate of the NMOS 24 and a VSS grounding terminal. Furthermore, a first parasitic diode 26 is formed at the PMOS 22, and a second parasitic diode 28 is formed at the NMOS 24. When static electricity discharges through any two points of the VDD power terminal, the bonding pad 12 and the VSS grounding terminal, the generated electrostatic currents will be instantly discharged by the activation of the first parasitic diode 26, the activation of the second parasitic diode 28, snapback breakdown generated by the PMOS 22, or snapback breakdown generated by the NMOS 24. For example, when a foreign object simultaneously touches the VDD power terminal and the bonding pad 12 and makes the electric potential of the bonding pad 12 higher than the electric potential of the VDD power terminal, the first parasitic diode 26 will be turned on for instantly discharging electrostatic currents. Likewise, when a foreign object simultaneously touches the bonding pad 12 and VSS grounding terminal and makes the electric potential of the bonding pad 12 higher than the electric potential of the VSS grounding terminal, the NMSO 24 will generate snapback breakdown for instantly discharging electrostatic currents. Please refer to U.S. Pat. No. 5,182,580 for more detailed information about the above-mentioned phenomenon of snapback breakdown. For brevity, further details are omitted here. However, with the continued scaling-down of semiconductor device dimensions, it is more difficult to control the phenomenon of snapback breakdown. In addition, when designing an ESD protection circuit for protecting an internal circuit from damage caused by electrostatic currents and in order to avoid having the ESD protection circuit burn itself out due to excess electrostatic currents, many factors must be considered. For example, an interval between the drain and the gate, the use of a salicide block (SAB), and the change of doping concentrations of wells, etc, must all be considered.
It is therefore a primary objective of the claimed invention to provide a simple ESD protection circuit for adjusting to the continuing scaling-down of semiconductor device dimensions.
The ESD protection circuit according to the claimed invention is formed on a P-type substrate and electrically connects to an internal circuit formed on the P-type substrate for protecting the internal circuit. The ESD protection circuit has a plurality of N-wells and a common discharge bar connected to a power terminal. The N-wells are formed in the P-type substrate, and in each of the N-wells, a P+ diffusion region and an N+ diffusion region are formed. The common discharge bar is electrically connected to all the N+ diffusion regions within the plurality of N-wells. Therein, each of the P+ diffusion within an N-well is electrically connected to a corresponding bonding pad.
In addition, the ESD protection circuit is also capable of being formed on an N-type substrate. In this condition, the ESD protection circuit has a plurality of P-wells and a common discharge bar connected to a grounding terminal. The P-wells are formed in the N-type substrate, and in each of the P-wells, an N+ diffusion region and a P+ diffusion region are formed. The common discharge bar is electrically connected to all the P+ diffusion regions within the plurality of P-wells. Therein, each of the N+ diffusion within a P-well is electrically connected to a corresponding bonding pad.
Therefore, an equivalent diode is formed in each of the N-wells or P-wells. When static electricity discharges from two bonding pads into two N-wells or P-wells, one of the equivalent diodes in the two N-wells or P-wells will be turned on by forward bias, and breakdown will be generated in another equivalent diode. Furthermore, a discharge path is generated for instantly discharging the static electricity.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.